The trend in modern microprocessor integrated circuits is to include large amounts of internal memory. This memory is known as "internal embedded memory" because it is located on the integrated circuit and has limited accessibility both logically and physically (there are usually many levels of logic and convoluted pathways of logic to be able to place or retrieve data to or from a memory location--and most modern fabrication methods bury the physical memory cells, or arrays of memory cells, into the lower layers of the integrated circuit so that there is no direct physical access to the arrays of memory). Embedded memory is very difficult to test and verify in all necessary test environments, most specifically, determining faults resulting from the silicon manufacturing process (fabrication test), determining faults due to the dicing and packaging process (manufacturing test), and determining faults that cause infant mortality due to the stresses of first applying power (voltage, current, and the effects of operating temperature) to the device.
Since the function of the memory is very critical to the overall integrated circuit function, it is very important to verify that the memory survives through the overall manufacturing process and still operates as it was intended to. This means that a high level of testing is required to identify memory problems, and more testing is required to locate the source of the problem so that any problem can be corrected. An appropriate level of testing is not always possible for embedded memories unless specific test logic and architectures are included during the design process.
Historically, when smaller amounts of memory were embedded on integrated circuits (such as a single memory), the memory was made directly accessible to the manufacturing tester through the package pins (and usually the exact bus that fed the memory was the chip level data and address bus). This allowed many "external" test algorithms from the board test environment to be used (boards that contain only memory chips are a special class of testing known as "memory testing" and are connected directly up to memory testers). These algorithms conduct fault detection inductively by writing and reading repeating patterns of ones and zero's in a graphical manner. This results in a physical picture of the memory (if it were possible to look at a memory as a collection of small squares connected in the horizontal and vertical directions) that looks like a checkerboard, or horizontal or vertical stripes, made of ones and zero's. These testing algorithms and methods were transferred to integrated circuit testing by including the ability to do this kind of testing with very expensive (roughly 3 million dollar) testers. These testers, however, placed design restrictions on the types and designs of memory testing that the testers could do (the tester had to have direct access and the standard algorithms were not effective if the path into the memory had a pipelined architecture).
As the amount of memory embedded on integrated circuits increased, the disadvantages of doing external testing, with very expensive testers that were not portable, and having to affect the memory architecture design negatively, caused the industry to find alternative ways to testing. The result was Built-in-Self-Test (BIST). The original goal of BIST was to allow internal testing of the embedded memory, but to not cost as much internal design and logic impact as making a tester interface (having all internal embedded memory locations somehow accessible to the external package connections that connect to the tester). This resulted in the basic method that is the general state of the art in memory testing, the single memory with a pattern generator on the data input, a pattern generator on the address control input, and a signature analyzer on the data output. The reason that this is the predominant form of internal embedded memory testing is because it has a standardized design form that can be applied generically during the design phase. Even though the above method has been widely used in the art, it has a lot of major disadvantages.
The "single" memory BIST testing method basically requires that a single memory (an array of memory cells that have a contiguous address space and data space with identical word widths--and are usually made physically to be located in one area) have a Linear feed Back Shift Register (LFSR) placed across the data input signal lines and also requires that a counter or LFSR be placed across the address signal lines. The data output signal lines are required to have an LFSR configured as a data compressor (signature analyzer) connected to them. At a minimum, this requires that one LFSR bit be used for each data signal line for the input and one LFSR bit be used for each data signal output line. The address lines can be the Data LFSR or a separate device. This means for a 32-bit data bus, 32 input sequential devices and 32 output sequential devices are required at a minimum. This input side must also have a method to apply these 32-bits so a multiplexer or the sequential device must sit right in the functional path which negatively impacts the functional performance. The output side can have the device in the output path or attached in a parallel manner so that the data can be siphoned off. Either way this negatively affects the functional performance.
The biggest disadvantage to this kind of BIST testing, is that the ordered algorithmic type of testing that is available from the tester interface, is not available from an LFSR. A counter can be created that will address the memories in the right sequence, but the data supplied for writing comes from an LFSR which produces a pseudo-random set of data. There are many papers published describing the "statistical" coverage that can be had by using pseudo-random data and with conducting pseudo-random address sequences. These limitations come about because the LFSR is relied on to conduct testing.
The LFSR in its basic form is a standard design element that consists of an N-bit shift register that has some of its output signals brought back to the beginning of N-bit shift register through Exclusive-Or (XOR) logic circuitry. It operates by shifting a stream of bits from one end to the other (for example from the left-most bit towards the right-most bit). The state of all of the bits and the applied input signals all factor into the next state of the register.
When used as a pattern generator the device is known as a PRPG LFSR or Pseudo-Random Pattern Generator Linear Feedback Shift Register (since it will always repeat a set of patterns for a given initial state it is not entirely random but pseudo-random). The feedback for a PRPG is usually chosen to be a maximal polynomial which just means that the feedback is implemented in such a way as to cause the register to cycle through all possible 2.sup.N states except the all zero state (e.g., for a 3 bit register N=3 so 2.sup.N is 8 -minus the zero state 000 is 7 different states). A pattern generator does not have any external input, but starts from a fixed state (the seed) and continues through the sequence of all possible patterns at the rate of one pattern every time a clock signal is applied. This is what limits the type of data that can be placed into the memories for testing.
When PRPG is used for address control information, the resulting sequence of addresses is some non-ordered sequence. This means that the memory cannot be tested in a directed order based on its physical layout. Since memory faults are highly coupled to the exact physical topology, it is impossible to match a standard LFSR data and address sequence to exercise the most probable failure mechanisms.
When an LFSR is used for pattern compression, it is known as a signature analyzer. In this case, there is an initial state (a seed) and external input to the device. Each clock cycle captures the input and operates on it based on the state of the register and the feedback designed in.
The disadvantages of this kind of testing is that it does not effectively cover the memory for the type of faults that are predominant, the pattern generation units take up a large amount of physical area, as does the compression unit, and only one memory is tested. In integrated circuit designs with more than one memory, this entire scheme is wrapped around each individual memory (one pattern generator, address controller, and signature analyzer for each memory). This is a very inefficient use of integrated circuit area for such a low-effective test.
Several of the advances in the art have come from making the above method more effective. Extra circuitry has been added to give more flexibility to the PRPG patterns by allowing the changing of the seed or the feedback polynomial. Papers have been written discussing this method to increase coverage of random pattern resistant faults (1992 ITC--Generation of Vector Patterns through Reseeding of Multiple-Polynomial Linear Feedback Shift Registers, p120). Other methods have used the PRPG in conjunction with scan path registers placed on the data and address signals to "shift" patterns across these lines. One version of this method known as exhaustive random sequences (ERS) is described in the art. The ERS has the added disadvantage of separating the read and write (which should happen in two consecutive cycles) by the length of the scan chain (i.e. if it takes 32 shifts to load the scan path that feeds the data bus, then the memory has sat idle for 32 cycles before the data can be written in, and the same is true for the data written out, 32 clock cycles have to be used to collect the 32 bits of data).
All of the advances to this kind of BIST methodology cost in terms of circuit area and negatively impact circuit performance.